Performance analysis of a multiple-microprocessor system with shared memory

Abstract

As the complexity of the microprocessor applications is increasing, there is a widespread use of multiple-microprocessor systems. Unlike most of the recent researches which are focused on performance analysis of symmetrical multiple-microprocessor systems, this dissertation presents a queueing model, M/M/c with unidentical service rate, for the performance analysis of unsymmetrical multiple-microprocessor systems with shared memory. The performance model is based on flow equivalence technique. The multiple-microprocessor systems being considered consist of an arbitrary number of microprocessors sharing the common memory. Each microprocessor has unidentical processing rate. The response time calculated from our model agrees with that measured from the experiment. It is found out from the model that in the shared-memory multiple-microprocessor system having two microprocessors working under the traffic intensity of higher than 50%, the second microprocessor should have the processing capability of not less than 40% of the first microprocessor in order to achieve full benefit of the multiple-microprocessor system.